Tomasulo's Algorithm Simulator

Instruction Input

Clock Cycle

0

Instruction Latency

Instruction IS EXE WB Total
ADD/SUB 1 1 1 3
MUL 1 6 1 8
DIV 1 12 1 14
LOAD 1 2 (ADDR: 1, MEM: 1) 1 4
STORE 1 1 (ADDR: 1) 1 3

Reservation Station Status

Name Busy Op Vj Vk Qj Qk A

Instruction Status

Instruction Issue Exec Write Back Status

Register File Status

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Memory Status

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Execution Log